A Model Context Protocol server for EDA (Electronic Design Automation) tools, providing interfaces for Verilog simulation, formal verification, FSM generation, Karnaugh map solving, and code generation with LLM assistance
Critical gaps across all dimensions. 17 tools with minimal descriptions (most under 50 chars), no input parameter descriptions, missing output schemas, and no error handling guidance. Tool names lack consistent verb-noun patterns (io_mkdir, fv_by_vcf, sim_by_iverilog use prepositions; assert_solver_llm, assert_inserter_llm lack clarity on what 'solver' and 'inserter' mean). Parameters like 'script', 'spec', 'fv_dir' are ambiguous without descriptions. No validation, no recovery paths, no security considerations visible. This server reads like a research prototype, not production-grade tooling.
Analyze waveform in specification, identify signals and their changes, convert to text description
Insert assertions into SystemVerilog code using LLM based on specification
Analyze buggy SystemVerilog code with assertion failures using LLM to suggest fixes
convert kmap to expr
Generate FSM Template Code
Formal verification using SymbiYosys (SBY) software
Formal verification using VCF software
No input parameter descriptions. Parameters like 'script', 'spec', 'fv_dir', 'sim_dir', 'task_id' lack any explanation of what they accept, expected format, or constraints. LLMs cannot infer meaning from names alone.
No output schemas documented. Tools return lists, strings, or JSON without declaring structure. LLMs cannot plan downstream calls or extract required fields (e.g., task_id, file_path) for chaining.
| Scored | Grade | Overall | Spec posture | Rubric |
|---|---|---|---|---|
| 2026-09-23 | F | 35 | 2026-07-28+ | v2 |
Create directory recursively
Write content to file
Query MEIC framework results by task ID
Query RTLRepair framework results by task ID
Search protocol implementation code snippets from protocol database
Search similar code from code database based on description
Simulate Verilog using Icarus Verilog
ModelSim Simulation
Query UVLLM framework results by task ID
Write content to a file, all files are written under the base directory (default: SmartCraft/outputs)
Inconsistent naming conventions. Tools use prepositions (io_mkdir, fv_by_vcf, sim_by_iverilog, search_similar_code) instead of verb_noun pattern (create_directory, verify_with_vcf, simulate_with_iverilog). Names like 'uvllm', 'meic', 'rtlrepair' are acronyms with no action verb, LLMs cannot infer intent.
No error handling or recovery guidance. Tools return raw success/failure strings ('success', 'No response from LLM') without actionable next steps. LLMs cannot self-correct or retry intelligently.
Ambiguous parameter names without type suffixes. 'script' in io_mkdir means directory path; 'script' in search_similar_code means description. 'spec' in assert_solver_llm is a requirement string; 'spec' in search_protocol is a requirement string. No _id, _name, _path suffixes to disambiguate.