Loading ToolBench
MCP server for Logisim Evolution — design and verify digital circuits with an LLM.
Strong foundation with 25 well-named tools covering a coherent domain (circuit design/simulation). All tools have descriptions (avg 156 chars, within 10-1024 baseline). Input schemas are complete with typed parameters and descriptions. However, output schemas are undocumented, responses are inferred from code but not formally declared. Error handling is minimal; most tools lack recovery guidance. Tool composition is excellent (single responsibility, clear chaining via component IDs). Security is solid (no secrets in params, file-based I/O). Main gaps: no output schema documentation, sparse error messages, missing parameter constraints (enums for gate_type, format values).
Generic component placer. ``type_key`` is one of the keys in :data:`logisim_mcp.circ.library.SPEC_FACTORIES` — e.g. ``"Multiplexer"``, ``"Adder"``, ``"Register"``, ``"Counter"``, ``"Constant"``, ``"Clock"``.
Add a logic gate (AND/OR/NAND/NOR/XOR/XNOR/NOT/BUF). Returns the component id (its location string) and the resolved location so the caller can wire it up.
Add an input or output Pin to ``circuit`` with the given label. Inputs face east (data flows out of the pin into the circuit); outputs face west. ``bit_width`` is the bus width (1 for a single wire).
Add a new empty circuit named ``name`` to the project.
Add a named tunnel (wireless connection node). Two tunnels with the same label in the same circuit are electrically one net. Great for clean schematics with many crossings.
Add a wire segment (or an L-shaped pair) between two grid points.
Output schemas undocumented. Tools return dicts (e.g., add_pin returns {id, loc, label, is_output}) but no formal schema is declared. LLMs cannot plan downstream calls or extract fields reliably.
Enum constraints missing for string parameters. gate_type accepts 'AND|OR|NAND|NOR|XOR|XNOR|NOT|BUF' but is defined as free-form string. simulate_tty format accepts 'table|tty|halt|speed|stats|tabbed|csv|bin|hex' but no enum. LLMs may hallucinate invalid values.
Error handling lacks recovery guidance. Tools raise FileNotFoundError, KeyError, etc. but do not return actionable error messages. E.g., 'no such file: /path' gives no hint to retry or check the path. Agents cannot self-correct.
| Scored | Grade | Overall | Spec posture | Rubric |
|---|---|---|---|---|
| 2026-09-23 | C | 61 | 2026-07-28+ | v2 |
Build a 1-bit full-adder (A, B, Cin → Sum, Cout).
Build a 1-bit half-adder (A, B → Sum, Cout) inside ``circuit_name``. Layout: pins on the left, XOR/AND on the right, output pins on the far right. Fan-out from A/B uses tunnels.
Build an N-bit ripple-carry adder using the built-in ``Adder`` component. Inputs are buses ``A`` and ``B`` of width ``bits``; outputs are ``Sum`` (``bits`` wide) and ``Cout``. This is much faster than chaining individual full-adders and matches what students typically use in coursework.
High-level connect — looks up port coordinates and routes an L-wire. ``from_id`` / ``to_id`` are component ids (``"(x,y)"`` strings as returned by ``add_gate`` / ``add_component``). ``from_port`` and ``to_port`` are port labels listed in ``library.ComponentSpec.ports`` (e.g. ``"in0"``, ``"in1"``, ``"out"``, ``"sum"``, ``"cin"``, ``"D"``, ``"clk"``).
Re-save an older ``.circ`` in the current Logisim Evolution format.
Open a ``.circ`` headless and return a component-class histogram. Wraps ``--tty stats`` — Logisim parses the file end-to-end, so exit code 0 also proves the schematic is structurally valid (no unknown libraries, no missing required attributes). Useful as a smoke test when end-to-end simulation isn't practical (e.g. sequential circuits).
Create a new empty Logisim ``.circ`` file at ``path``. The file contains a single circuit named ``main_circuit`` and the standard library list (Wiring, Gates, Plexers, Arithmetic, Memory, I/O, Base). Returns the absolute path of the created file.
Delete a circuit. Refuses to delete the main circuit.
Return a text netlist of a circuit (or the project's main circuit). Use this to introspect a circuit before editing it: you'll see every pin, every component, and every net (with the ports it connects).
Describe every circuit in a project (concise).
Return only the circuit names in ``path`` (small, cheap call).
Read a ``.circ`` file and return a summary of its circuits. Use this before any other operation to verify the file is well-formed and to discover circuit names.
Remove the component whose location string matches ``component_id``.
Rename a circuit. The ``main`` reference is updated too if needed.
Run the test bench embedded inside a ``.circ`` (``--test-circuit``). Exit code 0 means the test bench reached its ``Halt`` (success); any other exit code means it failed.
Run a Logisim test vector against a circuit. ``vector_path`` is a Logisim ``.vec`` file: first line is the header with pin labels (``[N]`` suffix for buses), subsequent lines are value rows (``0``, ``1``, ``0xFF``, ``x`` for don't-care).
Mark ``name`` as the project's main (top-level) circuit.
Run a circuit headless via ``--tty <format>``. The circuit must contain a ``TTY`` component (from ``#I/O``) for the interactive ``tty`` format, or a ``Halt`` component for tests. For purely combinational checks you typically want ``format='table'``.
Verify a circuit against an inline truth table. Args mirror what an LLM would naturally pass: lists of pin names and rows of values. Internally we write a temporary ``.vec`` file and delegate to :func:`run_test_vector`. Each row must be ``len(inputs) + len(outputs)`` items: input values first (the values to drive), then expected output values. ``"x"`` means don't-care.
Destructive operations (delete_circuit, remove_component) lack confirmation or dry-run support. An agent could accidentally delete a circuit without a safety gate. No idempotency guarantees documented.
Parameter constraints undocumented. bits (1-32), select_bits, timeout (seconds), x/y coordinates lack min/max bounds in descriptions. LLMs may pass invalid values (e.g., bits=1000, timeout=-1).