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WEFT Elaborates FPGA Toolchains - an MCP server for the Intel Quartus Prime flow
WEFT has 21 tools with reasonable naming (verb_noun pattern) and moderate descriptions (avg ~150 chars), but critical gaps undermine quality. Input schemas are present but lack type definitions for most parameters, only 'type' and 'description' fields visible, no 'type' values like 'string', 'integer', 'array'. Parameter descriptions are minimal (10-30 chars), far below the 72-char baseline. No output schemas documented. Error handling is absent, no recovery guidance, no categorization. Security concerns: no evidence of secret injection for Quartus credentials. Tool composition is reasonable (single responsibility), but missing pagination for list_* tools and no idempotent hints on reversible operations.
Cancel a running compilation job
Create a Quartus project
Generate documentation from compilation results
Generate documentation from constraints and reports
Generate documentation for a module
Get the hierarchy of modules in a design
Get log output from a compilation job
Input schemas lack type definitions. Parameters show only 'description' field; no 'type' (string, integer, array, object) visible in schema definitions. This violates JSON Schema and prevents LLM parameter validation.
Parameter descriptions are minimal (10 - 30 chars), far below the 72-char baseline. Examples: 'project name' (14 chars), 'job identifier' (14 chars), 'search query' (12 chars). LLMs cannot infer constraints, formats, or valid ranges from these.
| Scored | Grade | Overall | Spec posture | Rubric |
|---|---|---|---|---|
| 2026-09-23 | D | 52 | 2026-07-28+ | v2 |
Get the status of a compilation job
Get information about an indexed module or entity
Get information about a Quartus project
Index a PDF document for search
Index HDL sources in a directory for symbol search
Lint HDL sources without simulating them. Verilator handles Verilog and SystemVerilog, GHDL handles VHDL, and a design written in both is checked one language at a time with the rest named in excluded. linter=questa checks it whole with the vendor front-end, if one is configured -- a compile check rather than a style linter.
List documents available for indexing
List Quartus projects in the workspace
Parse Quartus compilation reports
Search indexed HDL symbols
Search indexed documents
Set project assignments through the Quartus Tcl API
Build and run a testbench. The simulator follows from the sources' suffixes unless one is named. No open simulator reads Verilog and VHDL in one run, so a source set spanning both is narrowed to the language of the testbench and the files left out are listed in the result; without a testbench to choose by, such a set is refused.
Start a Quartus compilation job
No output schemas documented. LLMs cannot plan downstream tool calls or extract required fields (e.g., job_id from start_compile for use in get_job_status). This breaks tool composition.
No error handling guidance. Tools provide no recovery hints, error categorization, or actionable messages. An LLM receiving a failure has no guidance on retry, user input, or next steps.
No pagination support on list_* tools. list_projects and list_indexed_docs lack limit/offset/cursor parameters and total count in response. Large result sets will blow context windows.