Loading ToolBench
Standalone MCP server that exposes the ECE Tool Suite bench to AI agents: instrument control (scope/DMM/spectrum analyzer/PSU), design calculators, power-stage verification, RTL analysis, MCU programming, and parts search.
ECE Tool Suite has 20 well-named, domain-specific tools with clear descriptions (avg 156 chars, within baseline 194). All tools have input schemas with types and descriptions. However, output schemas are not documented, LLMs cannot predict return structures for chaining. Parameter descriptions are present but often lack constraints (enums, ranges, formats). Error handling is minimal; no recovery guidance. Security: raw SCPI tool bypasses safety gates with audit logging, but no permission checks or scope declarations. Composition is strong, tools are single-responsibility and well-ordered (discovery → measurement → design). STDIO transport caps protocol readiness at 50.
Discover and connect instruments, assigning each to its role (scope/dmm/sa/psu/awg/eload). Set lan=True to also sweep the network via mDNS/LXI.
Size input+output capacitor banks for a buck/boost stage on a candidate cap: RMS ripple current, parallel-count for ripple + capacitance, ESR loss, temperature rise, output/input ripple voltage, and voltage-derating PASS/FAIL. First-order model — verify vs the cap datasheet.
Which EDA/MCU/power design tools are installed on this PC (CubeMX, CubeProgrammer, TI Power Stage Designer, UniFlash, CCS, KiCad, Altium, LTspice) with their paths.
Take one multimeter reading (value + unit + function) from the connected DMM.
What's plugged in and whether the VISA layer can drive it (drivability + install hints).
List the built-in EE design calculators and their input fields.
Output schemas not documented. LLMs cannot predict return structures (fields, types, nesting) for downstream tool chaining. E.g., power_design returns 'candidate real TI ICs with datasheet links' but structure is opaque.
Parameter constraints missing. Numeric params (fsw_khz, ripple_pct, iout) lack min/max bounds. String params (topology, role, dielectric) lack enum declarations. LLMs may pass invalid values (negative frequency, invalid topology).
No error recovery guidance. Tools lack actionable error messages. E.g., scpi warns 'raw writes bypass safety gates' but provides no guidance on what to do if a command fails or how to verify safety.
| Scored | Grade | Overall | Spec posture | Rubric |
|---|---|---|---|---|
| 2026-09-23 | C | 62 | 2026-07-28+ | v2 |
List the bench instruments the app currently has connected, with vendor/model/provenance.
OpenMagnetics/MKF magnetics design: searches a real multi-vendor core/material/wire DB for an inductor of the given inductance carrying a DC-biased triangular current, returns the top core + winding designs with physics-computed core (Steinmetz/iGSE) and copper (skin/proximity) losses. A datasheet-grade starting point — verify saturation/thermal margin against the core datasheet.
Flash/EEPROM size, architecture and programming interface for a supported MCU (e.g. 'atmega4809', 'attiny1616').
Dump a target MCU's flash (firmware) through an attached debugger. Returns the byte count and hex dump.
Connected MCU debuggers/programmers (Curiosity Nano / Atmel-ICE / SNAP / PICkit) + count of supported devices. pymcuprog-backed.
Parse a STM32CubeMX .ioc project: MCU, peripherals, pin assignments (signal/mux + GPIO label) and timer configs. Pass the .ioc file contents.
WEBENCH-class native power designer: auto-selects the topology (buck/boost/buck-boost/LDO; flyback when isolated=True — isolation is an explicit input, not inferred) for the Vin/Vout/Iout envelope, returns candidate real TI ICs with datasheet links, passive sizing, and a type-II compensation starting point. Verify the chosen sizing with power_verify before trusting it.
Closed-loop stability check (python-control): builds the current-mode buck loop with the designed type-II compensator and returns the ACHIEVED crossover, phase margin and gain margin (PASS/FAIL). Ri/Vref are IC-specific modeling assumptions — a design-review sanity check, not a measured margin; confirm on the bench.
Buck or boost power-stage design: duty, inductor, peak/input current, output cap.
Verify a buck/boost power-stage design by running a transient SPICE sim (LTspice/ngspice) and checking measured output ripple, inductor-ripple % and efficiency against targets. Returns PASS/FAIL per check plus the measured metrics.
Run a design calculator by id (e.g. 'trace_width', 'led_resistor', 'lc_resonant') with its numeric params. Use list_calculators() to see ids and fields.
Full oscilloscope measurement set (Vpp/Vrms/freq/period/duty/rise/fall…) for a channel.
Send a raw SCPI command to a connected instrument (role = scope/dmm/sa/psu/awg/eload). By default this is a QUERY and returns the instrument's response. Pass write=True to send a command that has no response. WARNING: raw writes bypass the app's safety gates — an output-enable or level command can energize your DUT. Every command is audit-logged.
Return the spectrum analyzer's peak marker (frequency + amplitude), via a raw query.
No permission checks or scope declarations. scpi tool allows raw SCPI writes with only audit logging, no permission gate. No tools declare required scopes (read:instrument, write:psu, etc.). Agents cannot be configured with least-privilege access.
STDIO transport only. Server is not remotely accessible and cannot be used by hosted MCP clients. Limits deployment to local/desktop use only.