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AI-assisted MCP server and Python SDK for AMD Vivado FPGA workflows
GateFlow has 22 tools with reasonable naming (verb_noun pattern) and structured schemas. However, descriptions are inconsistent, many are generic or lack actionable context. Parameter descriptions exist but are often minimal. Output schemas are partially documented via Pydantic models (BDResult, PS7PresetResult, etc.) but not consistently exposed in tool definitions. Error handling is minimal; most tools lack recovery guidance. The server mixes domain-specific FPGA tools (bd_create_ps7, create_clock) with generic file operations (create_file, delete_file), which dilutes focus. No tool annotations (readOnlyHint, destructiveHint) despite clear risk levels. Overall: functional but below production quality.
追加内容到文件。
创建 Zynq PS7 IP 实例。 创建 Processing System7 IP，可选择应用预设配置。
列出所有可用的 Zynq PS7 预设配置。 返回常见开发板的预设配置列表，可用于快速配置 PS7。
启用 PS7 的 AXI 端口。 启用指定的 AXI 主/从接口。
设置 PS7 的 Fabric 时钟。 配置 PS7 的 FCLK (Fabric Clock) 输出。
复制文件。
创建新的 Block Design。 此工具用于创建一个新的 Vivado Block Design。Block Design 是 Vivado 中 用于图形化设计 IP 集成的主要方式。
Status tools (embedded_status, vitis_status, xsct_status) have minimal descriptions ('查询 ... 模块状态') that do not explain what state is returned, when to call them, or what the output structure is. LLMs cannot determine when to use these vs other discovery tools.
File operation tools (create_file, delete_file, copy_file) lack explicit error handling and recovery guidance. delete_file is DESTRUCTIVE but has no confirmation step or dry-run option. No guidance on what to do if a file already exists or path is invalid.
No tool annotations (readOnlyHint, destructiveHint, idempotentHint) despite clear risk levels. delete_file is DESTRUCTIVE, bd_list_ps7_presets is READ_ONLY, but these are not declared in the tool definition. LLMs cannot reason about side effects.
Inferred effective spec: <=2025-11-25.
| Scored | Grade | Overall | Spec posture | Rubric |
|---|---|---|---|---|
| 2026-09-23 | D | 52 | <=2025-11-25 | v2 |
创建时钟约束。 此工具用于创建主时钟约束，定义设计中的时钟信号特性。 时钟约束是时序分析的基础，必须在综合前设置。
创建新文件。 创建指定路径的文件，可选择是否覆盖已存在的文件。
创建派生时钟约束。 此工具用于创建派生时钟（Generated Clock），派生时钟是从主时钟 通过分频、倍频或相位变换得到的时钟信号。
删除文件。
查询 embedded 非工程软件闭环模块状态。
列出目录中的文件。
打开现有的 Block Design。 此工具用于打开一个已存在的 Block Design 进行编辑。
读取文件内容。 读取指定路径的文件内容，支持读取部分行。
编译 standalone app 并输出 `.elf`。
定位或创建 standalone app 对应 BSP。
基于 `.xsa` 创建 standalone app。
从已有 Vivado `.xpr` 导出最小 `.xsa`。
查询 Vitis/XSA 导出模块状态。
创建或准备 XSCT workspace 目录。
查询 XSCT 软件构建模块状态。
Parameter descriptions are often minimal or missing context. E.g., bd_ps7_set_fclk 'frequency' param says '频率 (MHz)，范围 10-250' but does not explain consequences of invalid values or how to choose a frequency. No guidance on dependencies (e.g., FCLK_CLK0 must be enabled before setting frequency).
Output schemas are defined as Pydantic models (BDResult, PS7PresetResult) but not consistently documented in tool descriptions. LLMs cannot see what fields to expect without reading source code. No pagination support for list tools (bd_list_ps7_presets returns all presets; no limit/offset).