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Model Context Protocol (MCP) server for Verilog and SystemVerilog development
mcp-verilog defines 7 tools with complete input schemas and descriptions. Naming follows verb_noun convention (verilog_lint, verilog_compile, etc.), which is clear and actionable. Descriptions are substantive (100-200 chars), explaining WHAT each tool does and WHEN to use it. However, output schemas are not documented, LLMs cannot predict return structure for downstream chaining. Parameters lack type constraints (e.g., compiler enum is present but ruleset is free-form string). Error handling is minimal; no recovery guidance or actionable error messages visible in source. The verilog_generate_tb tool modifies state (WRITE risk) but lacks confirmation/dry-run pattern. Overall solid naming and descriptions, but missing output documentation and error guidance typical of production tools.
Performs syntax validation and elaboration checking on Verilog files using iverilog or verilator without running full simulation.
Measures Verilog line coverage by building the testbench with Verilator --coverage and running it, then reporting per-file covered/total lines and uncovered line numbers. Testbench must $finish.
Generates a testbench skeleton (clock/reset harness, DUT instantiation, VCD dump, PASS/$finish) from a Verilog module's port list, with a TODO for design-specific assertions.
Lints Verilog / SystemVerilog source files using verible-verilog-lint and returns structured line, column, severity, and rule diagnostics.
Compiles and runs a behavioral testbench simulation using iverilog + vvp. Captures runtime assertions ($fatal), testbench errors, and protects against infinite loops with a timeout.
Returns active container or host execution runtime info and versions of iverilog, verilator, verible, and sv2v.
Output schemas not documented. LLMs cannot predict return structure (fields, types, nesting) for any tool, blocking downstream tool chaining and forcing exploratory calls.
verilog_generate_tb is a WRITE tool (modifies filesystem) but lacks dry-run, confirmation, or idempotent hint. Agents may accidentally overwrite testbenches without warning.
No error handling guidance in source. Tools return raw exit codes/stderr without actionable recovery hints (e.g., 'Compiler not found. Install iverilog via apt-get install iverilog').
| Scored | Grade | Overall | Spec posture | Rubric |
|---|---|---|---|---|
| 2026-09-23 | D | 58 | 2026-07-28+ | v2 |
Summarizes a VCD waveform file (from iverilog $dumpfile/$dumpvars runs) as token-capped per-signal toggle counts, time range, and timescale. No GUI needed.
Parameter 'ruleset' in verilog_lint is free-form string with no enum constraint. Should enumerate valid Verible rulesets (all, default, etc.) to prevent hallucinated values.
verilog_toolchain_info accepts empty input schema (no parameters). Description does not explain what runtime info is returned or how to interpret it.