agentic-asic defines 5 tools for EDA workflows (formal verification, FPGA synthesis, place-and-route, bitstream generation, programming). Tool names follow verb_noun convention (formal_prove, fpga_synth, fpga_place_route, fpga_bitstream, fpga_program). Descriptions are present (avg ~80 chars) but lack actionable context for LLM selection. Input schemas are visible with type declarations and descriptions for most parameters. Critical gaps: (1) No output schemas documented, LLMs cannot plan downstream calls or extract results. (2) Parameters like 'mode', 'family', 'board' lack enum constraints, inviting hallucinated values. (3) Error handling is absent, no recovery guidance or categorization. (4) Irreversible operations (fpga_program) lack dry-run confirmation or safety gates. (5) No pagination or result limits documented. Baseline: 90% of A+ tools have documented return types; this server has zero. Average param description length is 72 chars; most here are 30-50 chars, below baseline.

• Add output schemas for all 5 tools. Document return types, field names, and structure. E.g., formal_prove should return {status: 'pass'|'fail', proof_time_s: number, counterexample?: object}.
• Convert 'mode' parameter in formal_prove to enum: ['bmc', 'prove']. Convert 'family' in fpga_synth/fpga_place_route to enum: ['ice40', 'ecp5', 'nexus', ...]. Convert 'board' in fpga_place_route to enum: ['icebreaker', 'tinyfpga_bx', ...].
• Add dry-run confirmation to fpga_program. Require explicit dry_run=false or a confirmation step before flashing. Document that dry_run=true is the safe default.
• Expand parameter descriptions to 80-120 chars. Add format hints: 'depth: integer, 1-1000, controls BMC unrolling depth'; 'cwd: absolute or relative path to working directory'.
• Implement error categorization. Return structured errors: {error_code: string, message: string, category: 'retryable'|'user_fixable'|'fatal', recovery_hint: string}. E.g., 'Verilog syntax error in top_module. Check syntax and retry.'